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» Critical path reduction for scalar programs
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CORR
2010
Springer
122views Education» more  CORR 2010»
13 years 5 months ago
Facility Location with Client Latencies: Linear-Programming based Techniques for Minimum-Latency Problems
We introduce a problem that is a common generalization of the uncapacitated facility location (UFL) and minimum latency (ML) problems, where facilities not only need to be opened ...
Deeparnab Chakrabarty, Chaitanya Swamy
IEEEPACT
2002
IEEE
13 years 10 months ago
Eliminating Exception Constraints of Java Programs for IA-64
Java exception checks are designed to ensure that any faulting instruction causing a hardware exception does not terminate the program abnormally. These checks, however, impose so...
Kazuaki Ishizaki, Tatsushi Inagaki, Hideaki Komats...
DSD
2009
IEEE
126views Hardware» more  DSD 2009»
13 years 9 months ago
Architecture-Driven Synthesis of Reconfigurable Cells
In this paper, we present a novel method for merging sets of computational patterns into a reconfigurable cell respecting design constraints and optimizing specific design aspects...
Christophe Wolinski, Krzysztof Kuchcinski, Erwan R...
ICCD
2004
IEEE
119views Hardware» more  ICCD 2004»
14 years 2 months ago
Simultaneous Scheduling, Binding and Layer Assignment for Synthesis of Vertically Integrated 3D Systems
Three dimensional vertically integrated systems allow active devices to be placed on multiple device layers. In recent years, a number of research efforts have addressed physical ...
Madhubanti Mukherjee, Ranga Vemuri
ISQED
2005
IEEE
125views Hardware» more  ISQED 2005»
13 years 11 months ago
A New Method for Design of Robust Digital Circuits
As technology continues to scale beyond 100nm, there is a significant increase in performance uncertainty of CMOS logic due to process and environmental variations. Traditional c...
Dinesh Patil, Sunghee Yun, Seung-Jean Kim, Alvin C...