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» Crosstalk at the Dynamic Node of Domino CMOS Circuits
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ISLPED
2000
ACM
91views Hardware» more  ISLPED 2000»
13 years 10 months ago
High-speed dynamic logic styles for scaled-down CMOS and MTCMOS technologies
A new high-speed Domino circuit, called HS-Domino is developed. HS-Domino resolves the trade-o between performance and noise margins in conventional CD-Domino logic while dissipat...
Mohamed W. Allam, Mohab Anis, Mohamed I. Elmasry
ISCAS
1999
IEEE
110views Hardware» more  ISCAS 1999»
13 years 10 months ago
Noise-tolerant dynamic circuit design
-- Noise in deep submicron technology combined with the move towards dynamic circuit techniques for higher performance have raised concerns about reliability and energyefficiency o...
Lei Wang, Naresh R. Shanbhag
DAC
2005
ACM
14 years 7 months ago
Designing logic circuits for probabilistic computation in the presence of noise
As Si CMOS devices are scaled down into the nanoscale regime, current computer architecture approaches are reaching their practical limits. Future nano-architectures will confront...
Kundan Nepal, R. Iris Bahar, Joseph L. Mundy, Will...
ISPD
1999
ACM
128views Hardware» more  ISPD 1999»
13 years 10 months ago
Transistor level micro-placement and routing for two-dimensional digital VLSI cell synthesis
There is an increasing need in modern VLSI designs for circuits implemented in high-performance logic families such as Cascode Voltage Switch Logic, Pass Transistor Logic, and dom...
Michael A. Riepe, Karem A. Sakallah
CEC
2005
IEEE
13 years 11 months ago
Dynamic power minimization during combinational circuit testing as a traveling salesman problem
Testing of VLSI circuits can cause generation of excessive heat which can damage the chips under test. In the random testing environment, high-performance CMOS circuits consume sig...
Artem Sokolov, Alodeep Sanyal, L. Darrell Whitley,...