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RTAS
2010
IEEE
13 years 3 months ago
Timing Analysis for TDMA Arbitration in Resource Sharing Systems
Abstract--Modern computing systems have adopted multicore architectures and multiprocessor systems on chip (MPSoCs) for accommodating the increasing demand on computation power. Ho...
Andreas Schranzhofer, Jian-Jia Chen, Lothar Thiele
ISPD
2006
ACM
68views Hardware» more  ISPD 2006»
13 years 12 months ago
Solving hard instances of floorplacement
Physical Design of modern systems on chip is extremely challenging. Such digital integrated circuits often contain tens of millions of logic gates, intellectual property blocks, e...
Aaron N. Ng, Igor L. Markov, Rajat Aggarwal, Venky...
ICS
2005
Tsinghua U.
13 years 11 months ago
A NUCA substrate for flexible CMP cache sharing
We propose an organization for the on-chip memory system of a chip multiprocessor, in which 16 processors share a 16MB pool of 256 L2 cache banks. The L2 cache is organized as a n...
Jaehyuk Huh, Changkyu Kim, Hazim Shafi, Lixin Zhan...
PVLDB
2008
123views more  PVLDB 2008»
13 years 5 months ago
Efficient implementation of sorting on multi-core SIMD CPU architecture
Sorting a list of input numbers is one of the most fundamental problems in the field of computer science in general and high-throughput database applications in particular. Althou...
Jatin Chhugani, Anthony D. Nguyen, Victor W. Lee, ...
SAMOS
2004
Springer
13 years 11 months ago
Scalable Instruction-Level Parallelism.
This paper presents a model for instruction-level distributed computing that allows the implementation of scalable chip multiprocessors. Based on explicit microthreading it serves ...
Chris R. Jesshope