ISPD 2006 - PDF Preprint Papers

ISPD 2006 International Symposium on Physical Design

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ISPD
2006
ACM

175views Hardware» more ISPD 2006»

mPL6: enhanced multilevel mixed-size placement

13 years 10 months ago

Download cadlab.cs.ucla.edu

The multilevel placement package mPL6 combines improved implementations of the global placer mPL5 (ISPD05) and the XDP legalizer and detailed placer (ASPDAC06). It consistently pr...

Tony F. Chan, Jason Cong, Joseph R. Shinnerl, Kent...

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Id	Views	Title	Status

1	175	mPL6: enhanced multilevel mixed-size placement	claim
2	158	Effective linear programming based placement methods
3	156	Improved method of cell placement with symmetry constraints for analog IC layout design	claim
4	151	Robust extraction of spatial correlation	claim
5	126	Noise driven in-package decoupling capacitor optimization for power integrity	claim
6	108	Statistical clock tree routing for robustness to process variations	claim
7	107	Clockless IC design using handshake technology	claim
8	103	High accurate pattern based precondition method for extremely large power/ground grid analysis	claim
9	102	A faster implementation of APlace	claim
10	91	Variation tolerant buffered clock network synthesis with cross links	claim
11	90	Fast buffer insertion considering process variations	claim
12	87	introduction to electromigration-aware physical design	claim
13	87	Floorplan and power/ground network co-synthesis for fast design convergence	claim
14	84	Efficient generation of short and fast repeater tree topologies	claim
15	84	Integrated retiming and simultaneous Vdd/Vth scaling for total power minimization	claim
16	83	Optimal partitioned fault-tolerant bus layout for reducing power in nanometer designs	claim
17	79	Non-gaussian statistical parameter modeling for SSTA with confidence interval analysis	claim
18	78	Efficient decoupling capacitor planning via convex programming methods	claim
19	71	Satisfying whitespace requirements in top-down placement	claim
20	70	Probabilistic evaluation of solutions in variability-driven optimization	claim
21	68	Solving hard instances of floorplacement	claim
22	66	Timing analysis in presence of supply voltage and temperature variations	claim

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