21 search results - page 1 / 5 » DAOmap: a depth-optimal area optimization mapping algorithm ... |
ICCAD
2004
IEEE
14 years 1 months ago
2004
IEEE
In this paper we study the technology mapping problem for FPGA architectures to minimize chip area, or the total number of lookup tables (LUTs) of the mapped design, under the chi...
FPGA
2006
ACM
13 years 8 months ago
2006
ACM
The paper presents several improvements to state-of-theart in FPGA technology mapping exemplified by a recent advanced technology mapper DAOmap [Chen and Cong, ICCAD `04]. Improve...
DAC
1996
ACM
13 years 9 months ago
1996
ACM
In this paper, we study the problem of decomposing gates in fanin-unbounded or K-bounded networks such that the K-input LUT mapping solutions computed by a depthoptimal mapper hav...
DAC
2006
ACM
14 years 5 months ago
2006
ACM
Both technology mapping and circuit clustering have a large impact on FPGA designs in terms of circuit performance, area, and power dissipation. Existing FPGA design flows carry o...
DAC
1993
ACM
13 years 9 months ago
1993
ACM
In this paper we study the area and depth trade-off in LUT based FPGA technology mapping. Starting from a depth-optimal mapping solution, we perform a number of depth relaxation o...