7 search results - page 1 / 2 » DPPC: Dynamic power partitioning and capping in chip multipr... |
ICCD
2011
IEEE
12 years 4 months ago
2011
IEEE
—A key challenge in chip multiprocessor (CMP) design is to optimize the performance within a power budget limited by the CMP’s cooling, packaging, and power supply capacities. ...
ICCD
2007
IEEE
13 years 8 months ago
2007
IEEE
While Speculative Multithreading (SM) on a Chip Multiprocessor (CMP) has the ability to speed-up hard-toparallelize applications, the power inefficiency of aggressive speculation ...
EUC
2006
Springer
13 years 8 months ago
2006
Springer
Multicore processors promise higher throughput at lower power consumption than single core processors. Thus in the near future they will be widely used in hard real-time systems as...
ISPASS
2005
IEEE
13 years 10 months ago
2005
IEEE
Today’s general-purpose processors are increasingly using multithreading in order to better leverage the additional on-chip real estate available with each technology generation...
HIPEAC
2009
Springer
13 years 8 months ago
2009
Springer
Shrinking process technologies and growing chip sizes have profound effects on process variation. This leads to Chip Multiprocessors (CMPs) where not all cores operate at maximum f...