Sciweavers

109 search results - page 2 / 22
» Data cache locking for higher program predictability
Sort
View
DAC
2010
ACM
13 years 5 months ago
Instruction cache locking using temporal reuse profile
The performance of most embedded systems is critically dependent on the average memory access latency. Improving the cache hit rate can have significant positive impact on the per...
Yun Liang, Tulika Mitra
DATE
2003
IEEE
94views Hardware» more  DATE 2003»
13 years 10 months ago
Reducing Power Consumption for High-Associativity Data Caches in Embedded Processors
Modern embedded processors use data caches with higher and higher degrees of associativity in order to increase performance. A set–associative data cache consumes a significant...
Dan Nicolaescu, Alexander V. Veidenbaum, Alexandru...
PDCN
2004
13 years 6 months ago
Speculative prefetching of optional locks in distributed systems
We present a family of methods for speeding up distributed locks by exploiting the uneven distribution of both temporal and spatial locality of access behaviour of many applicatio...
Thomas Schöbel-Theuer
ICS
2003
Tsinghua U.
13 years 10 months ago
Inferential queueing and speculative push for reducing critical communication latencies
Communication latencies within critical sections constitute a major bottleneck in some classes of emerging parallel workloads. In this paper, we argue for the use of Inferentially...
Ravi Rajwar, Alain Kägi, James R. Goodman
IEEEPACT
2003
IEEE
13 years 10 months ago
Miss Rate Prediction across All Program Inputs
Improving cache performance requires understanding cache behavior. However, measuring cache performance for one or two data input sets provides little insight into how cache behav...
Yutao Zhong, Steve Dropsho, Chen Ding