491 search results - page 1 / 99 » Data communication estimation and reduction for reconfigurab... |
DAC
2003
ACM
14 years 5 months ago
2003
ACM
Widespread adoption of reconfigurable devices requires system level synthesis techniques to take an application written in a high level language and map it to the reconfigurable d...
DAGSTUHL
2006
13 years 6 months ago
2006
Dynamic and partial reconfiguration discovers more and more the focus in academic and industrial research. Modern systems in e.g. avionic and automotive applications exploit the p...
ERSA
2009
13 years 2 months ago
2009
- The FPGA (re)configuration is a time-consuming process and a bottleneck in FPGA-based Run-Time Reconfigurable (RTR) systems. In this paper, we present a High Level Synthesis (HLS...
ARC
2006
Springer
13 years 8 months ago
2006
Springer
Abstract. Memory accesses contribute sunstantially to aggregate system delays. It is critical for designers to ensure that the memory subsystem is designed efficiently, and much wo...
FPL
2004
Springer
13 years 10 months ago
2004
Springer
A high-performance reconfigurable coarse-grain data-path, part of a hybrid reconfigurable platform, is introduced. The data-path consists of coarse grain components that their flex...