67 search results - page 1 / 14 » Data transformations enabling loop vectorization on multithr... |
PPOPP
2010
ACM
14 years 2 months ago
2010
ACM
Loop vectorization, a key feature exploited to obtain high performance on Single Instruction Multiple Data (SIMD) vector architectures, is significantly hindered by irregular memo...
NPC
2010
Springer
13 years 3 months ago
2010
Springer
Achieving high performance on today’s architectures requires careful orchestration of many optimization parameters. In particular, the presence of shared-caches on multicore arch...
IPPS
2010
IEEE
13 years 2 months ago
2010
IEEE
The memory hierarchy of most multicore systems contains one or more levels of cache that is shared among multiple cores. The shared-cache architecture presents many opportunities f...
DATE
2006
IEEE
13 years 11 months ago
2006
IEEE
Reduced energy consumption is one of the most important design goals for embedded application domains like wireless, multimedia and biomedical. Instruction memory hierarchy has be...
ISCA
2008
IEEE
13 years 11 months ago
2008
IEEE
The current trend is for processors to deliver dramatic improvements in parallel performance while only modestly improving serial performance. Parallel performance is harvested th...