Sciweavers

113 search results - page 3 / 23
» Database Architecture Optimized for the New Bottleneck: Memo...
Sort
View
CODES
2005
IEEE
13 years 11 months ago
Memory access optimizations in instruction-set simulators
Design of programmable processors and embedded applications requires instruction-set simulators for early exploration and validation of candidate architectures. Interpretive simul...
Mehrdad Reshadi, Prabhat Mishra
IEEEPACT
2006
IEEE
13 years 11 months ago
Whole-program optimization of global variable layout
On machines with high-performance processors, the memory system continues to be a performance bottleneck. Compilers insert prefetch operations and reorder data accesses to improve...
Nathaniel McIntosh, Sandya Mannarswamy, Robert Hun...
ICDE
2006
IEEE
206views Database» more  ICDE 2006»
14 years 7 months ago
Query Co-Processing on Commodity Hardware
The rapid increase in the data volumes for the past few decades has intensified the need for high processing power for database and data mining applications. Researchers have acti...
Anastassia Ailamaki, Naga K. Govindaraju, Dinesh M...
PCI
2005
Springer
13 years 11 months ago
Tuning Blocked Array Layouts to Exploit Memory Hierarchy in SMT Architectures
Cache misses form a major bottleneck for memory-intensive applications, due to the significant latency of main memory accesses. Loop tiling, in conjunction with other program tran...
Evangelia Athanasaki, Kornilios Kourtis, Nikos Ana...
SIGGRAPH
1994
ACM
13 years 9 months ago
FBRAM: a new form of memory optimized for 3D graphics
FBRAM, a new form of dynamic random access memory that greatly accelerates the rendering of Z-buffered primitives, is presented. Two key concepts make this acceleration possible. ...
Michael F. Deering, Stephen A. Schlapp, Michael G....