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» Dataflow Architectures for GALS
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ENTCS
2008
89views more  ENTCS 2008»
13 years 4 months ago
Dataflow Architectures for GALS
In Kahn process network (KPN), the processes (nodes) communicate by unbounded unidirectional FIFO channels (arcs), with the property of non-blocking writes and blocking reads on t...
Syed Suhaib, Deepak Mathaikutty, Sandeep K. Shukla
ISCA
1989
IEEE
1033views Hardware» more  ISCA 1989»
13 years 9 months ago
Can Dataflow Subsume von Neumann Computing?
: We explore the question: “What can a von Neumann processor borrow from dataflow to make it more suitable for a multiprocessor?’’ Starting with a simple, “RISC-like” ins...
Rishiyur S. Nikhil
FPL
2003
Springer
109views Hardware» more  FPL 2003»
13 years 10 months ago
Globally Asynchronous Locally Synchronous FPGA Architectures
Abstract. Globally Asynchronous Locally Synchronous (GALS) Systems have provoked renewed interest over recent years as they have the potential to combine the benefits of asynchron...
Andrew Royal, Peter Y. K. Cheung
ASAP
1997
IEEE
155views Hardware» more  ASAP 1997»
13 years 8 months ago
An Approach for Quantitative Analysis of Application-Specific Dataflow Architectures
In this paper we present an approach for quantitative analysis of application-specific dataflow architectures. The approach allows the designer to rate design alternatives in a qu...
Bart Kienhuis, Ed F. Deprettere, Kees A. Vissers, ...
ISSS
2000
IEEE
128views Hardware» more  ISSS 2000»
13 years 9 months ago
Hardware Synthesis from SPDF Representation for Multimedia Applications
Even though high-level hardware synthesis from dataflow graphs becomes popular in designing DSP systems, currently used dataflow models are inefficient to deal with emerging multi...
Chanik Park, Soonhoi Ha