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» Dealing with Transient Faults in the Interconnection Network...
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TPDS
2010
125views more  TPDS 2010»
12 years 11 months ago
Dealing with Transient Faults in the Interconnection Network of CMPs at the Cache Coherence Level
The importance of transient faults is predicted to grow due to current technology trends of increased scale of integration. One of the components that will be significantly affecte...
Ricardo Fernández Pascual, José M. G...
DSN
2008
IEEE
13 years 11 months ago
A fault-tolerant directory-based cache coherence protocol for CMP architectures
Current technology trends of increased scale of integration are pushing CMOS technology into the deepsubmicron domain, enabling the creation of chips with a significantly greater...
Ricardo Fernández Pascual, José M. G...
TPDS
2008
134views more  TPDS 2008»
13 years 4 months ago
Extending the TokenCMP Cache Coherence Protocol for Low Overhead Fault Tolerance in CMP Architectures
It is widely accepted that transient failures will appear more frequently in chips designed in the near future due to several factors such as the increased integration scale. On th...
Ricardo Fernández Pascual, José M. G...
HPCA
2007
IEEE
14 years 5 months ago
A Low Overhead Fault Tolerant Coherence Protocol for CMP Architectures
It is widely accepted that transient failures will appear more frequently in chips designed in the near future due to several factors such as the increased integration scale. On t...
Ricardo Fernández Pascual, José M. G...
ISCA
2002
IEEE
115views Hardware» more  ISCA 2002»
13 years 9 months ago
SafetyNet: Improving the Availability of Shared Memory Multiprocessors with Global Checkpoint/Recovery
We develop an availability solution, called SafetyNet, that uses a unified, lightweight checkpoint/recovery mechanism to support multiple long-latency fault detection schemes. At...
Daniel J. Sorin, Milo M. K. Martin, Mark D. Hill, ...