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HPCA
2009
IEEE
14 years 6 months ago
Design and implementation of software-managed caches for multicores with local memory
Heterogeneous multicores, such as Cell BE processors and GPGPUs, typically do not have caches for their accelerator cores because coherence traffic, cache misses, and latencies fr...
Sangmin Seo, Jaejin Lee, Zehra Sura
SIGECOM
2003
ACM
174views ECommerce» more  SIGECOM 2003»
13 years 11 months ago
Collaboration software to reduce inventory and increase response
Some recent trends in business and manufacturing hold the promise of greater profits, yet, due to profit-robbing inventory increases, this promise has not been fully realized. [9]...
Indu Bingham, Barbara Hoefle, Kim Phan, Jim Sizemo...
HIPC
1999
Springer
13 years 10 months ago
Process Migration Effects on Memory Performance of Multiprocessor
Abstract. In this work we put into evidence how the memory performance of a WebServer machine may depend on the sharing induced by process migration. We considered a shared-bus sha...
Pierfrancesco Foglia, Roberto Giorgi, Cosimo Anton...
IEEEPACT
2002
IEEE
13 years 11 months ago
Transparent Threads: Resource Sharing in SMT Processors for High Single-Thread Performance
Simultaneous Multithreading (SMT) processors achieve high processor throughput at the expense of single-thread performance. This paper investigates resource allocation policies fo...
Gautham K. Dorai, Donald Yeung
MICRO
2000
IEEE
176views Hardware» more  MICRO 2000»
13 years 5 months ago
An Advanced Optimizer for the IA-64 Architecture
level of abstraction, compared with the program representation for scalar optimizations. For example, loop unrolling and loop unrolland-jam transformations exploit the large regist...
Rakesh Krishnaiyer, Dattatraya Kulkarni, Daniel M....