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» Defect tolerance for nanocomputer architecture
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ISVLSI
2006
IEEE
149views VLSI» more  ISVLSI 2006»
13 years 11 months ago
Defect-Aware Design Paradigm for Reconfigurable Architectures
With advances in process technology, the feature sizes are decreasing, which leads to higher defect densities. More sophisticated techniques, at increased costs are required to av...
Rahul Jain, Anindita Mukherjee, Kolin Paul
PRDC
2006
IEEE
13 years 11 months ago
SEVA: A Soft-Error- and Variation-Aware Cache Architecture
As SRAM devices are scaled down, the number of variation-induced defective memory cells increases rapidly. Combination of ECC, particularly SECDED, with a redundancy technique can...
Luong Dinh Hung, Masahiro Goshima, Shuichi Sakai
VLSID
2004
IEEE
117views VLSI» more  VLSID 2004»
14 years 6 months ago
Evaluating the Reliability of Defect-Tolerant Architectures for Nanotechnology with Probabilistic Model Checking
As we move from deep submicron technology to nanotechnology for device manufacture, the need for defect-tolerant architectures is gaining importance. This is because, at the nanos...
Gethin Norman, David Parker, Marta Z. Kwiatkowska,...
ASPLOS
2006
ACM
13 years 11 months ago
A defect tolerant self-organizing nanoscale SIMD architecture
Jaidev P. Patwardhan, Vijeta Johri, Chris Dwyer, A...
JETC
2007
63views more  JETC 2007»
13 years 5 months ago
A self-organizing defect tolerant SIMD architecture
Jaidev P. Patwardhan, Chris Dwyer, Alvin R. Lebeck