15 search results - page 2 / 3 » Delay Hazards in Complex Gate Based Speed Independent VLSI C... |
EH
2003
IEEE
13 years 10 months ago
2003
IEEE
This paper describes a multi-objective Evolutionary Algorithm (EA) system for the synthesis of efficient non-linear VLSI circuit modules. The EA takes the specification for a no...
ISVLSI
2002
IEEE
13 years 10 months ago
2002
IEEE
Retiming has been shown to be a powerful technique for improving the performance of synchronous circuits. However, even though retiming algorithms of polynomial time complexity ha...
ISCAS
2003
IEEE
13 years 10 months ago
2003
IEEE
We propose an algorithm based on singular value decomposition (SVD) to reduce the number of process variation variables. With few process variation variables, fault simulation and...
GLVLSI
2006
IEEE
13 years 11 months ago
2006
IEEE
In modern IC design, the number of long on-chip wires has been growing rapidly because of the increasing circuit complexity. Interconnect delay has dominated over gate delay as te...
VLSID
2002
IEEE
14 years 5 months ago
2002
IEEE
Interconnect delay has become a critical factor in determining the performance of integrated circuits. Routing and buffering are powerful means of improving the circuit speed and ...