15 search results - page 3 / 3 » Delay Hazards in Complex Gate Based Speed Independent VLSI C... |
ISQED
2005
IEEE
13 years 11 months ago
2005
IEEE
Abstract— Reliability enhancements are traditionally implemented through redundancies at the system level or through the use of harden-cell-designs at the circuit level. Reliabil...
FPGA
2003
ACM
13 years 10 months ago
2003
ACM
This paper presents a new power saving, high speed FPGA design enhancing a previous SiGe CML FPGA based on the Xilinx 6200 FPGA. The design aims at having a higher performance but...
MST
2002
13 years 5 months ago
2002
The poor scalability of existing superscalar processors has been of great concern to the computer engineering community. In particular, the critical-path lengths of many components...
FOCS
2000
IEEE
13 years 10 months ago
2000
IEEE
Randomness extractors convert weak sources of randomness into an almost uniform distribution; the conversion uses a small amount of pure randomness. In algorithmic applications, t...
VLSID
2006
IEEE
14 years 5 months ago
2006
IEEE
SoC design methodologies are under constant revision due to adoption of fast shrinking process technologies at nanometer levels. Nanometer process geometries exhibit new complex d...