A scalable 2 V, 20 GHz FPGA using SiGe HBT BiCMOS technology

This paper presents a new power saving, high speed FPGA design enhancing a previous SiGe CML FPGA based on the Xilinx 6200 FPGA. The design aims at having a higher performance but minimizing power consumption. The new SiGe process has traded off the circuit’s performance for reduced power consumption. The power supply voltage has been reduced from 3.4 V to 2.0 V. The structure of the Basic Cell, including the Configurable Logic Block (CLB) and routing multiplexers (MUXs), has been modified so that the supply voltage reduction can be attained. Simulations have shown that the gate delay of the new Basic Cell is reduced from 130 ps in the prior design to 51 ps. The total power consumption for each Basic Cell has been reduced 94% from 71 mW to 4.2 mW, making a large scale FPGA feasible. This design is currently under fabrication for testing. Categories and Subject Descriptors B.7.1D.3.3 [Integrated Circuit]: Types and Design Styles – Advanced Technology, Gate Arrays, VLSI (Very Large ...

• Type: Conference
• Year: 2003
• Where: FPGA
• Authors: Jong-Ru Guo, Chao You, Kuan Zhou, Bryan S. Goda, Russell P. Kraft, John F. McDonald
• Keywords: Basic Cell, FPGA 2003, Hardware, Power Consumption, SiGe CML FPGA