27 search results - page 2 / 6 » Delay Minimal Decomposition of Multiplexers in Technology Ma... |
ICCAD
1994
IEEE
13 years 8 months ago
1994
IEEE
We consider the problem of performance driven lookup-table (LUT) based technology mapping for FPGAs using a general delay model. In the general delay model, each interconnection e...
DAC
2006
ACM
14 years 5 months ago
2006
ACM
The gain-based technology mapping paradigm has been successfully employed for finding minimum delay and minimum area mappings. However, existing gain-based technology mappers fail...
ICCAD
1997
IEEE
13 years 8 months ago
1997
IEEE
In this paper, we present an optimal algorithm for solving the simultaneous technology mapping and linear placement problem for tree-structured circuits with the objective of mini...
ASPDAC
2004
ACM
13 years 10 months ago
2004
ACM
- Data path connection elements, such as multiplexers, consume a significant amount of area on a VLSI chip, especially for FPGA designs. Multiplexer optimization is a difficult pro...
DAC
1998
ACM
13 years 9 months ago
1998
ACM
Recently, functional decomposition has been adopted for LUT based FPGA technology mapping with good results. In this paper, we propose a novel method for functional multipleoutput...