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» Delay Minimal Decomposition of Multiplexers in Technology Ma...
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ICCAD
1999
IEEE
88views Hardware» more  ICCAD 1999»
13 years 9 months ago
Performance optimization under rise and fall parameters
Typically,cell parameterssuch as the pin-to-pinintrinsicdelays, load-dependentcoe cients,andinputpin capacitanceshavedifferent values for rising and falling signals. The performan...
Rajeev Murgai
DAC
2006
ACM
14 years 6 months ago
DAG-aware AIG rewriting a fresh look at combinational logic synthesis
This paper presents a technique for preprocessing combinational logic before technology mapping. The technique is based on the representation of combinational logic using And-Inve...
Alan Mishchenko, Satrajit Chatterjee, Robert K. Br...
ICCAD
2001
IEEE
111views Hardware» more  ICCAD 2001»
14 years 1 months ago
Congestion Aware Layout Driven Logic Synthesis
In this paper, we present novel algorithms that effectively combine physical layout and early logic synthesis to improve overall design quality. In addition, we employ partitionin...
Thomas Kutzschebauch, Leon Stok
IDA
2005
Springer
13 years 10 months ago
Learning Label Preferences: Ranking Error Versus Position Error
We consider the problem of learning a ranking function, that is a mapping from instances to rankings over a finite number of labels. Our learning method, referred to as ranking by...
Eyke Hüllermeier, Johannes Fürnkranz
PDPTA
2000
13 years 6 months ago
The PODOS File System - Exploiting the High-Speed Communication Subsystem
Performance Oriented Distributed Operating System (PODOS) is a clustering environment, being built on a monolithic Linux kernel. PODOS augments very few components to the Linux ke...
Sudharshan Vazhkudai, P. Tobin Maginnis