43 search results - page 2 / 9 » Delay-Insensitive Interface Specification and Synthesis |
CHES
2006
Springer
13 years 9 months ago
2006
Springer
Balanced dynamic dual-rail gates and asynchronous circuits have been shown, if implemented correctly, to have natural and efficient resistance to side-channel attacks. Despite thei...
POPL
2005
ACM
14 years 5 months ago
2005
ACM
While a typical software component has a clearly specified (static) interface in terms of the methods and the input/output types they support, information about the correct sequen...
LOPSTR
1998
Springer
13 years 9 months ago
1998
Springer
This paper describes a class of decision procedures that we have found useful for efficient, domain-specific deductive synthesis, and a method for integrating this type of procedur...
DATE
1998
IEEE
13 years 9 months ago
1998
IEEE
One of the main tasks within the high-level synthesis (HLS) process is the verification problem to prove automatically the correctness of the synthesis results. Currently, the res...
ICCAD
2005
IEEE
14 years 2 months ago
2005
IEEE
We present a new hardware synthesis methodology for guarded atomic actions (or rules), which satisfies performance-related scheduling specifications provided by the designer. The ...