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PATMOS
2007
Springer
13 years 11 months ago
Soft Error-Aware Power Optimization Using Gate Sizing
—Power consumption has emerged as the premier and most constraining aspect in modern microprocessor and application-specific designs. Gate sizing has been shown to be one of the...
Foad Dabiri, Ani Nahapetian, Miodrag Potkonjak, Ma...
ISPD
2006
ACM
68views Hardware» more  ISPD 2006»
13 years 11 months ago
Solving hard instances of floorplacement
Physical Design of modern systems on chip is extremely challenging. Such digital integrated circuits often contain tens of millions of logic gates, intellectual property blocks, e...
Aaron N. Ng, Igor L. Markov, Rajat Aggarwal, Venky...
IJCNN
2000
IEEE
13 years 9 months ago
Exploiting the Selfish Gene Algorithm for Evolving Cellular Automata
This paper shows an application in the field of Electronic CAD of the Selfish Gene algorithm, an evolutionary algorithm based on a recent interpretation of the Darwinian theory. Te...
Fulvio Corno, Matteo Sonza Reorda, Giovanni Squill...
ISPD
2004
ACM
146views Hardware» more  ISPD 2004»
13 years 10 months ago
Power-aware clock tree planning
Modern processors and SoCs require the adoption of poweroriented design styles, due to the implications that power consumption may have on reliability, cost and manufacturability ...
Monica Donno, Enrico Macii, Luca Mazzoni