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» Design and Analysis of a Robust Pipelined Memory System
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INFOCOM
2010
IEEE
13 years 3 months ago
Design and Analysis of a Robust Pipelined Memory System
Abstract—Many network processing applications require wirespeed access to large data structures or a large amount of flowlevel data, but the capacity of SRAMs is woefully inadeq...
Hao Wang, Haiquan (Chuck) Zhao, Bill Lin, Jun Xu
ISCA
1997
IEEE
135views Hardware» more  ISCA 1997»
13 years 9 months ago
The Design and Analysis of a Cache Architecture for Texture Mapping
The effectiveness of texture mapping in enhancing the realism of computer generated imagery has made support for real-time texture mapping a critical part of graphics pipelines. D...
Ziyad S. Hakura, Anoop Gupta
MICRO
2006
IEEE
145views Hardware» more  MICRO 2006»
13 years 11 months ago
Virtually Pipelined Network Memory
We introduce virtually-pipelined memory, an architectural technique that efficiently supports high-bandwidth, uniform latency memory accesses, and high-confidence throughput eve...
Banit Agrawal, Timothy Sherwood
HPCA
2000
IEEE
13 years 9 months ago
Design of a Parallel Vector Access Unit for SDRAM Memory Systems
We are attacking the memory bottleneck by building a “smart” memory controller that improves effective memory bandwidth, bus utilization, and cache efficiency by letting appl...
Binu K. Mathew, Sally A. McKee, John B. Carter, Al...
FCCM
2002
IEEE
171views VLSI» more  FCCM 2002»
13 years 10 months ago
Coarse-Grain Pipelining on Multiple FPGA Architectures
Reconfigurable systems, and in particular, FPGA-based custom computing machines, offer a unique opportunity to define application-specific architectures. These architectures offer...
Heidi E. Ziegler, Byoungro So, Mary W. Hall, Pedro...