Due to recent advances in microfluidics technology, digital microfluidic biochips and their associated CAD problems have gained much attention, most of which has been devoted to d...
Ping-Hung Yuh, Sachin S. Sapatnekar, Chia-Lin Yang...
As VLSI technology scales toward 65nm and beyond, both timing and power performance of integrated circuits are increasingly affected by process variations. In practice, people oft...
As the operation frequency reaches gigahertz in very deep-submicron designs, the effect of on-chip inductance on circuit performance can no longer be neglected. Therefore, it is d...
The wire length estimation is the bottleneck of packing based block placers. To cope with this problem, we present a fast wire length estimation method in this paper. The key idea...
This paper describes a technique that reduces dynamic power in FPGAs by reducing the number of glitches in the global routing resources. The technique involves adding programmable...
Julien Lamoureux, Guy G. Lemieux, Steven J. E. Wil...