57 search results - page 2 / 12 » Design and Implementation of Multiple Addresses Parallel Tra... |
CCGRID
2008
IEEE
13 years 6 months ago
2008
IEEE
We have been developing a Grid-enabled MPI communication library called GridMPI, which is designed to run on multiple clusters connected to a wide-area network. Some of these clust...
HOTI
2005
IEEE
13 years 10 months ago
2005
IEEE
High performance routers require substantial amounts of memory to store packets awaiting transmission, requiring the use of dedicated memory devices with the density and capacity ...
JSA
2010
12 years 11 months ago
2010
The high chip-level integration enables the implementation of large-scale parallel processing architectures with 64 and more processing nodes on a single chip or on an FPGA device...
ISCA
2008
IEEE
13 years 4 months ago
2008
IEEE
Network-on-Chip (NoC) architectures have been adopted by a growing number of multi-core designs as a flexible and scalable solution to the increasing wire delay constraints in the...
JSAC
2006
13 years 4 months ago
2006
The ability to inspect both packet headers and payloads to identify attack signatures makes network intrusion detection system (NIDS) a promising approach to protect Internet syste...