Design of Randomized Multichannel Packet Storage for High Performance Routers

High performance routers require substantial amounts of memory to store packets awaiting transmission, requiring the use of dedicated memory devices with the density and capacity to provide the required storage economically. The memory bandwidth required for packet storage subsystems often exceeds the bandwidth of individual memory devices, making it necessary to implement packet storage using multiple memory channels. This raises the question of how to design multichannel storage systems that make effective use of the available memory and memory bandwidth, while forwarding packets at link rate in the presence of arbitrary packet retrieval patterns. A recent series of papers has demonstrated an architecture that uses onchip SRAM to buffer packets going to/from a multichannel storage system, while maintaining high performance in the presence worst-case traffic patterns. Unfortunately, the amount of on-chip storage required grows as the product of the number of channels and the number o...

• Type: Conference
• Year: 2005
• Where: HOTI
• Authors: Sailesh Kumar, Patrick Crowley, Jonathan S. Turner
• Keywords: HOTI 2005, Multichannel Storage System, Packet Storage, Storage System