Sciweavers

127 search results - page 4 / 26
» Design and Implementation of Power-Aware Virtual Memory
Sort
View
DATE
2003
IEEE
128views Hardware» more  DATE 2003»
13 years 10 months ago
Virtual Compression through Test Vector Stitching for Scan Based Designs
We propose a technique for compressing test vectors. The technique reduces test application time and tester memory requirements by utilizing part of the predecessor response in co...
Wenjing Rao, Alex Orailoglu
VEE
2009
ACM
240views Virtualization» more  VEE 2009»
14 years 1 days ago
Memory buddies: exploiting page sharing for smart colocation in virtualized data centers
Many data center virtualization solutions, such as VMware ESX, employ content-based page sharing to consolidate the resources of multiple servers. Page sharing identifies virtual...
Timothy Wood, Gabriel Tarasuk-Levin, Prashant J. S...
DAC
2004
ACM
14 years 6 months ago
Virtual memory window for application-specific reconfigurable coprocessors
Reconfigurable Systems-on-Chip (SoCs) on the market consist of full-fledged processors and large Field-Programmable Gate-Arrays (FPGAs). The latter can be used to implement the sy...
Miljan Vuletic, Laura Pozzi, Paolo Ienne
FCCM
2004
IEEE
118views VLSI» more  FCCM 2004»
13 years 9 months ago
Virtual Memory Window for a Portable Reconfigurable Cryptography Coprocessor
Reconfigurable System-on-Chip (SoC) platforms that incorporate hard-core processors surrounded by large amounts of FPGA are today commodities: the reconfigurable logic is often us...
Miljan Vuletic, Laura Pozzi, Paolo Ienne
PCRCW
1997
Springer
13 years 9 months ago
ChaosLAN: Design and Implementation of a Gigabit LAN Using Chaotic Routing
In recent years, theChaos Project at theUniversityofWashingtonhas analyzed and simulated a dozen routing algorithms. Three new routing algorithms have been invented; of these, the...
Neil R. McKenzie, Kevin Bolding, Carl Ebeling, Law...