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VLSISP
2010
148views more  VLSISP 2010»
13 years 4 months ago
Energy-efficient Hardware Architecture and VLSI Implementation of a Polyphase Channelizer with Applications to Subband Adaptive
Abstract Polyphase channelizer is an important component of subband adaptive filtering systems. This paper presents an energy-efficient hardware architecture and VLSI implementatio...
Yongtao Wang, Hamid Mahmoodi, Lih-Yih Chiou, Hunso...
ICIP
2003
IEEE
14 years 7 months ago
Parallel-pipelined architecture for 2-D ICT VLSI implementation
The Integer Cosine Transform (ICT) has been shown to be an alternative to the DCT for image processing. This paper presents a parallel-pipelined architecture of an 8x8 ICT(10, 9, ...
Juan A. Michell, Gustavo A. Ruiz, Angel M. Buron
ISCAS
2006
IEEE
94views Hardware» more  ISCAS 2006»
13 years 11 months ago
Relaxed tree search MIMO signal detection algorithm design and VLSI implementation
Abstract— This paper presents an implementation-oriented breadthfirst tree search MIMO detector design solution. Techniques at algorithm and VLSI architecture levels are develop...
Sizhong Chen, Tong Zhang, M. Goel
ASPDAC
2007
ACM
116views Hardware» more  ASPDAC 2007»
13 years 9 months ago
VLSI Design of Multi Standard Turbo Decoder for 3G and Beyond
Turbo decoding architectures have greater error correcting capability than any other known code. Due to their excellent performance turbo codes have been employed in several trans...
Imran Ahmed, Tughrul Arslan
ICIP
1994
IEEE
14 years 7 months ago
Full Custom VLSI Implementation of High-Speed 2-D DCT/IDCT Chip
In this paper we present a full-custom VLSI design of highspeed 2-D DCT/IDCT processor based on the new class of time-recursive algorithms and architectures which has never been i...
Vishnu Srinivasan, K. J. Ray Liu