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» Design for Verification of the PCI-X Bus
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CORR
2007
Springer
127views Education» more  CORR 2007»
13 years 5 months ago
Common Reusable Verification Environment for BCA and RTL Models
This paper deals with a common verification methodology and environment for SystemC BCA and RTL models. The aim is to save effort by avoiding the same work done twice by different...
Giuseppe Falconeri, Walid Naifer, Nizar Romdhane
DAC
1991
ACM
13 years 9 months ago
REX - A VLSI Parasitic Extraction Tool for Electromigration and Signal Analysis
REX is a program that extracts parasitic resistance and capacitance values for nodes in VLSI layouts. REX also performs network serial and parallel simplifications. Two types of n...
Jerry P. Hwang
FDL
2005
IEEE
13 years 11 months ago
Implementation of a SystemC based Environment
Verification and validation are key issues for today's SoC design projects. This paper presents the implementation of a SystemC based environment for transaction-based verifi...
Richard Hoffer, Frank Baszynski
DAC
2007
ACM
14 years 6 months ago
An Embedded Multi-resolution AMBA Trace Analyzer for Microprocessor-based SoC Integration
The bus tracing is used to catch related signals for further investigation and analysis. However, the trace size of cycleaccurate tracing is large and the trace cycle is shallow u...
Chung-Fu Kao, Ing-Jer Huang, Chi-Hung Lin
DATE
2005
IEEE
164views Hardware» more  DATE 2005»
13 years 11 months ago
Automated Synthesis of Assertion Monitors using Visual Specifications
Automated synthesis of monitors from high-level properties plays a significant role in assertion-based verification. We present here a methodology to synthesize assertion monitors...
Ambar A. Gadkari, S. Ramesh