14 search results - page 1 / 3 » Design of Half-Rate Clock and Data Recovery Circuits for Opt... |
DAC
2001
ACM
14 years 5 months ago
2001
ACM
This paper describes the design of two half-rate clock and data recovery circuits for optical receivers. Targeting the data rate of 10-Gb/s, the rst implementation incorporates a ...
DATE
2000
IEEE
13 years 9 months ago
2000
IEEE
Clock and data recovery circuits are essential components in communication systems. They directly influence the bit-error-rate performance of communication links. It is desirable...
CCECE
2009
IEEE
13 years 9 months ago
2009
IEEE
A truly monolithic clock and data recovery (CDR) circuit for low cost low-end data communication systems has been realized in 0.6ȝm CMOS. The implemented CDR comprises a phase-an...
ISVLSI
2007
IEEE
13 years 11 months ago
2007
IEEE
Power line communications (PLC) using impulse ultra wideband (UWB) in a microprocessor had been proposed for ubiquitous access of internal nodes for test/debug purposes. In this p...
SLIP
2004
ACM
13 years 10 months ago
2004
ACM
Throughput, power consumption, signal integrity, pin count and routing complexity are all increasingly important interconnect issues that the system designer must deal with. Recen...