28 search results - page 1 / 6 » Design of Hierarchical Classifier with Hybrid Architectures |
PREMI
2005
Springer
13 years 10 months ago
2005
Springer
DATE
2006
IEEE
13 years 10 months ago
2006
IEEE
It is anticipated that self assembled ultra-dense nanomemories will be more susceptible to manufacturing defects and transient faults than conventional CMOS-based memories, thus t...
HPCA
2009
IEEE
14 years 5 months ago
2009
IEEE
Performance and power consumption of an on-chip interconnect that forms the backbone of Chip Multiprocessors (CMPs), are directly influenced by the underlying network topology. Bo...
JLP
2006
13 years 4 months ago
2006
In this paper, we develop a theory of modular design and refinement of hierarchical hybrid systems. In particular, we present compositional trace-based semantics for the language ...
IJCNN
2008
IEEE
13 years 11 months ago
2008
IEEE
—The system architecture presented in this paper is designed for helping an aged person to live longer independently in their own home by detecting unusual and potentially hazard...