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DSD
2010
IEEE
161views Hardware» more  DSD 2010»
13 years 4 months ago
Design of Trace-Based Split Array Caches for Embedded Applications
—Since many embedded systems execute a predefined set of programs, tuning system components to application programs and data is the approach chosen by many design techniques to o...
Alice M. Tokarnia, Marina Tachibana
DAC
2004
ACM
14 years 5 months ago
High level cache simulation for heterogeneous multiprocessors
As multiprocessor systems-on-chip become a reality, performance modeling becomes a challenge. To quickly evaluate many architectures, some type of high-level simulation is require...
Joshua J. Pieper, Alain Mellan, JoAnn M. Paul, Don...
EVOW
2011
Springer
12 years 7 months ago
Two Iterative Metaheuristic Approaches to Dynamic Memory Allocation for Embedded Systems
Abstract. Electronic embedded systems designers aim at finding a tradeoff between cost and power consumption. As cache memory management has been shown to have a significant imp...
María Soto, André Rossi, Marc Sevaux
CASES
2007
ACM
13 years 8 months ago
A low power front-end for embedded processors using a block-aware instruction set
Energy, power, and area efficiency are critical design concerns for embedded processors. Much of the energy of a typical embedded processor is consumed in the front-end since inst...
Ahmad Zmily, Christos Kozyrakis
CASES
2001
ACM
13 years 8 months ago
Energy-efficient instruction cache using page-based placement
Energy consumption is a crucial factor in designing batteryoperated embedded and mobile systems. The memory system is a major contributor to the system energy in such environments...
Hyun Suk Kim, Narayanan Vijaykrishnan, Mahmut T. K...