24 search results - page 4 / 5 » Design of a Feasible On-Chip Interconnection Network for a C... |
TC
2008
13 years 4 months ago
2008
The design and performance of next-generation chip multiprocessors (CMPs) will be bound by the limited amount of power that can be dissipated on a single die. We present photonic n...
HPCA
2007
IEEE
14 years 5 months ago
2007
IEEE
It is widely accepted that transient failures will appear more frequently in chips designed in the near future due to several factors such as the increased integration scale. On t...
ISPASS
2009
IEEE
13 years 11 months ago
2009
IEEE
Until very recently, microprocessor designs were computation-centric. On-chip communication was frequently ignored. This was because of fast, single-cycle on-chip communication. T...
PDP
2010
IEEE
13 years 9 months ago
2010
IEEE
In the last years high performance processor designs have evolved toward Chip-Multiprocessor (CMP) architectures that implement multiple processing cores on a single die. As the nu...
ISCA
2011
IEEE
12 years 8 months ago
2011
IEEE
Network-on-chip (NoC) has become a critical shared resource in the emerging Chip Multiprocessor (CMP) era. Most prior NoC designs have used the same type of router across the enti...