19 search results - page 1 / 4 » Design of a High-Throughput Distributed Shared-Buffer NoC Ro... |
NOCS
2010
IEEE
13 years 2 months ago
2010
IEEE
Router microarchitecture plays a central role in the performance of an on-chip network (NoC). Buffers are needed in routers to house incoming flits which cannot be immediately forw...
ICCD
2007
IEEE
14 years 1 months ago
2007
IEEE
As chip multiprocessors (CMPs) become the only viable way to scale up and utilize the abundant transistors made available in current microprocessors, the design of on-chip network...
PDP
2010
IEEE
13 years 3 months ago
2010
IEEE
— This paper presents Investigation of Transient Fault Effects in an asynchronous NoC router. The experiment is based on simulation-based fault injection method to assess the fau...
PDP
2010
IEEE
13 years 11 months ago
2010
IEEE
— Due to the multi-core processors, the importance of parallel workloads has increased considerably. However, manycore chips demand new interconnection strategies, since traditio...
ISCA
2008
IEEE
13 years 4 months ago
2008
IEEE
Network-on-Chip (NoC) architectures have been adopted by a growing number of multi-core designs as a flexible and scalable solution to the increasing wire delay constraints in the...