Sciweavers

PDP
2010
IEEE

Impact of Parallel Workloads on NoC Architecture Design

13 years 11 months ago
Impact of Parallel Workloads on NoC Architecture Design
— Due to the multi-core processors, the importance of parallel workloads has increased considerably. However, manycore chips demand new interconnection strategies, since traditional crossbars or buses, common for current multi-core processors, have problems related to wires and scalability. For this reason, Networks-on-Chip (NoCs) have been developed in order to support the performance and parallelism focused on several workloads. Although a Network-on-Chip is a good option, most designs consist of a large number of routers. These routers are responsible for forwarding packets, and consequently, for supporting message-passing workloads. In this context, the NoC performance is a problem. Therefore, the main goal of this paper is to evaluate the impact of well-known parallel workloads on NoC architecture design. In order to achieve high performance, the results point out to parallel workloads with small packets and cluster-based NoCs with circuit switching and adaptable topologies. NoC...
Henrique Cota de Freitas, Lucas Mello Schnorr, Mar
Added 17 May 2010
Updated 17 May 2010
Type Conference
Year 2010
Where PDP
Authors Henrique Cota de Freitas, Lucas Mello Schnorr, Marco Antonio Zanata Alves, Philippe Olivier Alexandre Navaux
Comments (0)