17 search results - page 1 / 4 » Design of a Massively Parallel Vision Processor based on Mul... |
ISCAS
2007
IEEE
13 years 11 months ago
2007
IEEE
— Increasing demands for robust image recognition systems require vision processors not only with enormous computational capacities but also with sufficient flexibility to hand...
ICPR
2004
IEEE
14 years 6 months ago
2004
IEEE
Parallel processors such as SIMD computers have been successfully used in various areas of high performance image and data processing. Due to their characteristics of highly regula...
JSA
2010
12 years 11 months ago
2010
The high chip-level integration enables the implementation of large-scale parallel processing architectures with 64 and more processing nodes on a single chip or on an FPGA device...
ISCAS
2003
IEEE
13 years 10 months ago
2003
IEEE
A new vision chip, SCAMP-2, has been developed in a 0.35µm CMOS technology. In this paper, the design of the chip is presented, with particular emphasis on its readout architectu...
LCN
2003
IEEE
13 years 10 months ago
2003
IEEE
The GigaNetIC project aims to develop high-speed components for networking applications based on massively parallel architectures. A central part of this project is the design, ev...