18 search results - page 3 / 4 » Design of a Single Event Upset (SEU) Mitigation Technique fo... |
DATE
2010
IEEE
13 years 11 months ago
2010
IEEE
Modern FPGAs have been designed with advanced integrated circuit techniques that allow high speed and low power performance, joined to reconfiguration capabilities. This makes new...
FPL
2006
Springer
13 years 9 months ago
2006
Springer
Reconfigurable architectures are becoming increasingly popular with space related design engineers as they are inherently flexible to meet multiple requirements and offer signific...
IOLTS
2003
IEEE
13 years 11 months ago
2003
IEEE
Fault tolerant design is a technique emerging in Integrated Circuits (IC’s) to deal with the increasing error susceptibility (Soft Errors, or Single Event Upsets, SEU) caused by...
ISLPED
2005
ACM
13 years 11 months ago
2005
ACM
Concerns about the reliability of real-time embedded systems that employ dynamic voltage scaling has recently been highlighted [1,2,3], focusing on transient-fault-tolerance techn...
FPGA
2010
ACM
14 years 17 days ago
2010
ACM
Triple Modular Redundancy (TMR) is a common reliability technique for mitigating single event upsets (SEUs) in FPGA designs operating in radiation environments. For FPGA systems t...