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SAC
1995
ACM
13 years 8 months ago
Design of a VLSI very high speed reconfigurable digital fuzzy processor
A trigger system in High Energy Physics Experiments (HEPE) has to decide, in few µs, if the data related to a nuclear event have to be stored or not. Normally, these data, are co...
Enzo Gandolfi, Alessandro Gabrielli, Massimo Maset...
ICIP
1994
IEEE
14 years 6 months ago
Full Custom VLSI Implementation of High-Speed 2-D DCT/IDCT Chip
In this paper we present a full-custom VLSI design of highspeed 2-D DCT/IDCT processor based on the new class of time-recursive algorithms and architectures which has never been i...
Vishnu Srinivasan, K. J. Ray Liu
ERSA
2006
197views Hardware» more  ERSA 2006»
13 years 6 months ago
A High Speed, Run Time Reconfigurable Image Acquisition processor for a Missile Approach Warning System
High frame rate video capture and image processing is an important capability for applications in defense and homeland security where incoming missiles must be detected in very sh...
Vinay Sriram, David Kearney
RECONFIG
2008
IEEE
225views VLSI» more  RECONFIG 2008»
13 years 11 months ago
A Hardware Filesystem Implementation for High-Speed Secondary Storage
Platform FPGAs are capable of hosting entire Linuxbased systems including standard peripherals, integrated network interface cards and even disk controllers on a single chip. File...
Ashwin A. Mendon, Ron Sass
ISJGP
2010
13 years 2 months ago
On the Hardware Implementation Cost of Crypto-Processors Architectures
A variety of modern technologies such as networks, Internet, and electronic services demand private and secure communications for a great number of everyday transactions. Security ...
Nicolas Sklavos