4 search results - page 1 / 1 » Design of an On-Chip Test Pattern Generator without Prohibit... |
VLSID
2002
IEEE
14 years 5 months ago
2002
IEEE
| This paper reports the design of a Test Pattern Generator (TPG) for VLSI circuits. The onchip TPG is so designed that it generates test patterns while avoiding generation of a gi...
VLSID
2003
IEEE
14 years 5 months ago
2003
IEEE
This paper introduces a Built-In Self Test (BIST) structure referred to as Universal BIST (UBIST). The Test Pattern Generator (TPG) of the proposed UBIST is designed to generate an...
VLSID
2005
IEEE
13 years 10 months ago
2005
IEEE
During pseudorandom testing, a significant amount of energy and test application time is wasted for generating and for applying “useless” test vectors that do not contribute t...
CIKM
2009
Springer
13 years 11 months ago
2009
Springer
In order to enable scalable querying of graph databases, intelligent selection of subgraphs to index is essential. An improved index can reduce response times for graph queries si...