2 search results - page 1 / 1 » Design of high-performance CMOS charge pumps in phase-locked... |
GLVLSI
2007
IEEE
13 years 12 months ago
2007
IEEE
In this paper, two new dual-path based area efficient loop filter circuits are proposed for Charge Pump Phase Locked Loop (CPPLL). The proposed circuits were designed in 0.25µ CS...
ISCAS
1999
IEEE
13 years 9 months ago
1999
IEEE
Practical considerations in the design of CMOS charge pumps are discussed. The non-ideal effects of the charge pump by the leakage current, the mismatch, and the delay offset in t...