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TECS
2008
122views more  TECS 2008»
13 years 5 months ago
Quantitative analysis of the speed/accuracy trade-off in transaction level modeling
tion. Transaction Level Modeling (TLM) has been proposed to abstract communication for highspeed system simulation and rapid design space exploration. Although being widely accepte...
Gunar Schirner, Rainer Dömer
CODES
2007
IEEE
13 years 11 months ago
Compile-time decided instruction cache locking using worst-case execution paths
Caches are notorious for their unpredictability. It is difficult or even impossible to predict if a memory access results in a definite cache hit or miss. This unpredictability i...
Heiko Falk, Sascha Plazar, Henrik Theiling
FCCM
2002
IEEE
156views VLSI» more  FCCM 2002»
13 years 10 months ago
MPEG-Compliant Entropy Decoding on FPGA-Augmented TriMedia/CPU64
The paper presents a Design Space Exploration (DSE) experiment which has been carried out in order to determine the optimum FPGA–based Variable-Length Decoder (VLD) computing re...
Mihai Sima, Sorin Cotofana, Stamatis Vassiliadis, ...