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NSDI
2004
13 years 7 months ago
Designing a DHT for Low Latency and High Throughput
Designing a wide-area distributed hash table (DHT) that provides high-throughput and low-latency network storage is a challenge. Existing systems have explored a range of solution...
Frank Dabek, Jinyang Li, Emil Sit, James Robertson...
ISCAS
1995
IEEE
91views Hardware» more  ISCAS 1995»
13 years 9 months ago
An FPGA Based Reconfigurable Coprocessor Board Utilizing a Mathematics of Arrays
Abstract -- Work in progress at the University of Missouri-Rolla on hardware assists for high performance computing is presented. This research consists of a novel field programmab...
W. Eatherton, J. Kelly, T. Schiefelbein, H. Pottin...
IOPADS
1996
100views more  IOPADS 1996»
13 years 7 months ago
ENWRICH a Compute-Processor Write Caching Scheme for Parallel File Systems
Many parallel scientific applications need high-performance I/O. Unfortunately, end-to-end parallel-I/O performance has not been able to keep up with substantial improvements in p...
Apratim Purakayastha, Carla Schlatter Ellis, David...
ECAI
2010
Springer
13 years 6 months ago
Optimal Task Migration in Service-Oriented Systems: Algorithms and Mechanisms
In service-oriented systems, such as grids and clouds, users are able to outsource complex computational tasks by procuring resources on demand from remote service providers. As th...
Sebastian Stein, Enrico Gerding, Nicholas R. Jenni...
RTAS
1997
IEEE
13 years 10 months ago
Scalable Hardware Priority Queue Architectures for High-Speed Packet Switches
ÐWith effective packet-scheduling mechanisms, modern integrated networks can support the diverse quality-of-service requirements of emerging applications. However, arbitrating bet...
Sung-Whan Moon, Kang G. Shin, Jennifer Rexford