19 search results - page 2 / 4 » Designing Regular Network-on-Chip Topologies under Technolog... |
IPPS
2003
IEEE
13 years 11 months ago
2003
IEEE
Tiled architectures can provide a model for early estimation of global interconnect costs. A design exploration tool for reconfigurable architectures is currently under developmen...
IEEEAMS
2002
IEEE
2002
IEEE
Understanding Consistency Maintenance in Service Discovery Architectures in Response to Message Loss
13 years 11 months ago
Current trends suggest future software systems will comprise collections of components that combine and recombine dynamically in reaction to changing conditions. Service-discovery...
ASAP
2005
IEEE
13 years 12 months ago
2005
IEEE
In this paper we introduce a design methodology that allows the system/circuit designer to build reliable systems out of unreliable nano-scale components. The central point of our...
NOCS
2009
IEEE
14 years 1 months ago
2009
IEEE
Design Constraints imposed by global interconnect delays as well as limitations in integration of disparate technologies make 3-D chip stacks an enticing technology solution for m...
ISCA
2005
IEEE
13 years 12 months ago
2005
IEEE
: The theoretical study of quantum computation has yielded efficient algorithms for some traditionally hard problems. Correspondingly, experimental work on the underlying physical...