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» Designing Reliable Algorithms in Unreliable Memories
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HPDC
2007
IEEE
14 years 3 days ago
Ridge: combining reliability and performance in open grid platforms
Large-scale donation-based distributed infrastructures need to cope with the inherent unreliability of participant nodes. A widely-used work scheduling technique in such environme...
Krishnaveni Budati, Jason D. Sonnek, Abhishek Chan...
ICC
2007
IEEE
14 years 3 days ago
On the Impact of Ignoring Markovian Channel Memory on the Analysis of Wireless Systems
– Recent wireless measurement studies have revealed the presence of high-order memory in wireless bit-error channels. However, most wireless studies continue to employ the memory...
Syed A. Khayam, Hayder Radha
ICCAD
2007
IEEE
137views Hardware» more  ICCAD 2007»
14 years 2 months ago
Combining static and dynamic defect-tolerance techniques for nanoscale memory systems
Abstract— Nanoscale technology promises dramatically increased device density, but also decreased reliability. With bit error rates projected to be as high as 10%, designing a us...
Susmit Biswas, Gang Wang, Tzvetan S. Metodi, Ryan ...
CASES
2004
ACM
13 years 11 months ago
Memory overflow protection for embedded systems using run-time checks, reuse and compression
Title of thesis: MEMORY OVERFLOW PROTECTION FOR EMBEDDED SYSTEMS USING RUN-TIME CHECKS, REUSE AND COMPRESSION Surupa Biswas, Master of Science, 2004 Thesis directed by: Assistant ...
Surupa Biswas, Matthew Simpson, Rajeev Barua
DAC
2008
ACM
14 years 6 months ago
On the role of timing masking in reliable logic circuit design
Soft errors, once only of concern in memories, are beginning to affect logic as well. Determining the soft error rate (SER) of a combinational circuit involves three main masking ...
Smita Krishnaswamy, Igor L. Markov, John P. Hayes