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» Designing systems-on-chip using cores
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SLIP
2006
ACM
13 years 11 months ago
Energy/area/delay trade-offs in the physical design of on-chip segmented bus architecture
— The increasing gap between design productivity and chip complexity and the emerging Systems-On-Chip (SOC) architectural template have led to the wide utilization of reusable ha...
Jin Guo, Antonis Papanikolaou, Pol Marchal, Franck...
ENGL
2008
100views more  ENGL 2008»
13 years 5 months ago
HIDE+: A Logic Based Hardware Development Environment
With the advent of System-On-Chip (SOC) technology, there is a pressing need to enhance the quality of ools available and increase the level of abstraction at which hardware is des...
Abdsamad Benkrid, Khaled Benkrid
DSD
2008
IEEE
124views Hardware» more  DSD 2008»
13 years 12 months ago
A Modular Approach to Model Heterogeneous MPSoC at Cycle Level
This paper proposes a system-level cycle-based framework to model and design heterogeneous Multiprocessor Systems on-Chip (MPSoC), called GRAPES. The approach features flexibilit...
Matteo Monchiero, Gianluca Palermo, Cristina Silva...
FDL
2005
IEEE
13 years 11 months ago
Automatic synthesis of the Hardware/Software Interface
Although Moore’s Law enables a huge number of components to be integrated into a single chip, design methods that will allow system architects to put the components together to ...
Francesco Regazzoni, André C. Nácul,...
FPT
2005
IEEE
163views Hardware» more  FPT 2005»
13 years 11 months ago
Designing an FPGA SoC Using a Standardized IP Block Interface
Designing Systems on-Chip is becoming increasingly popular as die sizes increase and technology sizes decrease. The complexity of integrating different types of Processing Element...
Lesley Shannon, Blair Fort, Samir Parikh, Arun Pat...