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» Designs for Reducing Test Time of Distributed Small Embedded...
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ISCA
2010
IEEE
336views Hardware» more  ISCA 2010»
13 years 10 months ago
Reducing cache power with low-cost, multi-bit error-correcting codes
Technology advancements have enabled the integration of large on-die embedded DRAM (eDRAM) caches. eDRAM is significantly denser than traditional SRAMs, but must be periodically r...
Chris Wilkerson, Alaa R. Alameldeen, Zeshan Chisht...
ICPP
2003
IEEE
13 years 11 months ago
Hardware-Assisted Design for Fast Packet Forwarding in Parallel Routers
A hardware-assisted design, dubbed cache-oriented multistage structure (COMS), is proposed for fast packet forwarding. COMS incorporates small on-chip cache memory in its constitu...
Nian-Feng Tzeng
LCTRTS
1999
Springer
13 years 10 months ago
Optimizing for Reduced Code Space using Genetic Algorithms
Code space is a critical issue facing designers of software for embedded systems. Many traditional compiler optimizations are designed to reduce the execution time of compiled cod...
Keith D. Cooper, Philip J. Schielke, Devika Subram...
INFOCOM
1999
IEEE
13 years 10 months ago
Techniques for Optimizing CORBA Middleware for Distributed Embedded Systems
The distributed embedded systems industry is poised to leverage emerging real-time operating systems, such as Inferno, Windows CE 2.0, and Palm OS, to support mobile communication...
Aniruddha S. Gokhale, Douglas C. Schmidt
TVLSI
2008
133views more  TVLSI 2008»
13 years 6 months ago
Test Data Compression Using Selective Encoding of Scan Slices
We present a selective encoding method that reduces test data volume and test application time for scan testing of Intellectual Property (IP) cores. This method encodes the slices ...
Zhanglei Wang, Krishnendu Chakrabarty