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DATE
2005
IEEE
122views Hardware» more  DATE 2005»
13 years 10 months ago
Diagnostic and Detection Fault Collapsing for Multiple Output Circuits
We discuss fault equivalence and dominance relations for multiple output combinational circuits. The conventional definition for equivalence says that “Two faults are equivalen...
Raja K. K. R. Sandireddy, Vishwani D. Agrawal
ICCAD
2006
IEEE
134views Hardware» more  ICCAD 2006»
14 years 1 months ago
A delay fault model for at-speed fault simulation and test generation
We describe a transition fault model, which is easy to simulate under test sequences that are applied at-speed, and provides a target for the generation of at-speed test sequences...
Irith Pomeranz, Sudhakar M. Reddy
IOLTS
2009
IEEE
174views Hardware» more  IOLTS 2009»
13 years 11 months ago
ATPG-based grading of strong fault-secureness
—Robust circuit design has become a major concern for nanoscale technologies. As a consequence, for design validation, not only the functionality of a circuit has to be considere...
Marc Hunger, Sybille Hellebrand, Alejandro Czutro,...
DDECS
2007
IEEE
86views Hardware» more  DDECS 2007»
13 years 11 months ago
Design and Analysis of a New Self-Testing Adder which Utilizes Polymorphic Gates
— This paper describes a new self-testing 1-bit full adder. This circuit consists of three polymorphic NAND/NOR gates, two XOR gates and two inverters. The adder is able to detec...
Lukás Sekanina
ITC
1993
IEEE
110views Hardware» more  ITC 1993»
13 years 9 months ago
Novel Test Pattern Generators for Pseudo-Exhaustive Testing
ÐPseudoexhaustive testing of a combinational circuit involves applying all possible input patterns to all its individual output cones. The testing ensures detection of all detecta...
Rajagopalan Srinivasan, Sandeep K. Gupta, Melvin A...