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ISCAS
2006
IEEE
81views Hardware» more  ISCAS 2006»
13 years 11 months ago
Digit-serial/parallel multipliers with improved throughput and latency
––Digit-serial/parallel multipliers with improved throughput and latency are presented. The multipliers are based on unfolded bit-serial/parallel multipliers. The unfolding yie...
Magnus Karlsson, Mark Vesterbacka
ICCD
2007
IEEE
200views Hardware» more  ICCD 2007»
14 years 1 months ago
A parallel IEEE P754 decimal floating-point multiplier
Decimal floating-point multiplication is important in many commercial applications including banking, tax calculation, currency conversion, and other financial areas. This paper...
Brian J. Hickmann, Andrew Krioukov, Michael J. Sch...
ISCAS
2007
IEEE
99views Hardware» more  ISCAS 2007»
13 years 11 months ago
A Parallel Architecture for Hermitian Decoders: Satisfying Resource and Throughput Constraints
— Hermitian Codes offer desirable properties such as large code lengths, good error-correction at high code rates, etc. The main problem in making Hermitian codes practical is to...
Rachit Agarwal, Emanuel M. Popovici, Brendan O'Fly...
MASCOTS
2010
13 years 3 months ago
Exploiting Concurrency to Improve Latency and throughput in a Hybrid Storage System
—This paper considers the problem of how to improve the performance of hybrid storage system employing solid state disks and hard disk drives. We utilize both initial block alloc...
XiaoJian Wu, A. L. Narasimha Reddy
IPPS
2009
IEEE
13 years 11 months ago
Double Throughput Multiply-Accumulate unit for FlexCore processor enhancements
— As a simple five-stage General-Purpose Processor (GPP), the baseline FlexCore processor has a limited set of datapath units. By utilizing a flexible datapath interconnect and...
Tung Thanh Hoang, Magnus Själander, Per Larss...