58 search results - page 11 / 12 » Digit-serial parallel multipliers with improved throughput a... |
HPCA
2011
IEEE
12 years 9 months ago
2011
IEEE
Traditional architectural designs are normally focused on CPUs and have been often decoupled from I/O considerations. They are inefficient for high-speed network processing with a...
QEST
2007
IEEE
14 years 1 days ago
2007
IEEE
Previous studies have shown that buffering packets in DRAM is a performance bottleneck. In order to understand the impediments in accessing the DRAM, we developed a detailed Petri...
HOTI
2005
IEEE
13 years 11 months ago
2005
IEEE
Cluster based server architectures have been widely used as a solution to overloading in web servers because of their cost effectiveness, scalability and reliability. A content aw...
HPCA
2008
IEEE
14 years 6 months ago
2008
IEEE
Interconnection networks-on-chip (NOCs) are rapidly replacing other forms of interconnect in chip multiprocessors and system-on-chip designs. Existing interconnection networks use...
IEEEPACT
2005
IEEE
13 years 11 months ago
2005
IEEE
Current integration trends embrace the prosperity of single-chip multi-core processors. Although multi-core processors deliver significantly improved system throughput, single-thr...