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» Digital circuit design through simulated evolution (SimE)
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ET
2010
113views more  ET 2010»
13 years 3 months ago
Calibration and Test Time Reduction Techniques for Digitally-Calibrated Designs: an ADC Case Study
Modern mixed-signal/RF circuits with a digital calibration capability could achieve significant performance improvement through calibration. However, the calibration process often ...
Hsiu-Ming Chang, Kuan-Yu Lin, Kwang-Ting (Tim) Che...
ICCAD
1997
IEEE
137views Hardware» more  ICCAD 1997»
13 years 9 months ago
Optimization techniques for high-performance digital circuits
The relentless push for high performance in custom digital circuits has led to renewed emphasis on circuit optimization or tuning. The parameters of the optimization are typically...
Chandramouli Visweswariah
ISCAS
2007
IEEE
79views Hardware» more  ISCAS 2007»
13 years 12 months ago
Impact of strain on the design of low-power high-speed circuits
- In this article, we explore the impact of strain on circuit performance when strained silicon (s-Si) devices are used for designing low-power high-speed circuits. Emphasis has be...
H. Ramakrishnan, K. Maharatna, S. Chattopadhyay, A...
JUCS
2007
208views more  JUCS 2007»
13 years 5 months ago
The Architecture and Circuital Implementation Scheme of a New Cell Neural Network for Analog Signal Processing
: It is a difficult problem that using cellular neural network to make up of analog signal processing circuit. This paper presented the architecture of new cellular neural network ...
Youren Wang, Zhiqiang Zhang, Jiang Cui
PATMOS
2005
Springer
13 years 11 months ago
Design of Variable Input Delay Gates for Low Dynamic Power Circuits
The time taken for a CMOS logic gate output to change after one or more inputs have changed is called the output delay of the gate. A conventional multi-input CMOS gate is designed...
Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bush...