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» Disclosing the LDPC code decoder design space
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DATE
2008
IEEE
120views Hardware» more  DATE 2008»
14 years 6 days ago
A Case Study in Reliability-Aware Design: A Resilient LDPC Code Decoder
Chip reliability becomes a great threat to the design of future microelectronic systems with the continuation of the progressive downscaling of CMOS technologies. Hence increasing...
Matthias May, Matthias Alles, Norbert Wehn
TCOM
2010
111views more  TCOM 2010»
13 years 4 months ago
Design of irregular LDPC codes with optimized performance-complexity tradeoff
—The optimal performance-complexity tradeoff for error-correcting codes at rates strictly below the Shannon limit is a central question in coding theory. This paper proposes a nu...
Benjamin Smith, Masoud Ardakani, Wei Yu, Frank R. ...
SIPS
2008
IEEE
14 years 3 days ago
Unified decoder architecture for LDPC/turbo codes
Low-density parity-check (LDPC) codes on par with convolutional turbo codes (CTC) are two of the most powerful error correction codes known to perform very close to the Shannon li...
Yang Sun, Joseph R. Cavallaro
ICC
2007
IEEE
107views Communications» more  ICC 2007»
14 years 2 days ago
Error Floors of LDPC Coded BICM
Abstract— In recent years performance prediction for communication systems utilizing iteratively decodable codes has been of considerable interest. There have been significant b...
Aditya Ramamoorthy, Nedeljko Varnica
ASAP
2006
IEEE
147views Hardware» more  ASAP 2006»
13 years 7 months ago
Reconfigurable Shuffle Network Design in LDPC Decoders
Several semi-parallel decoding architectures have been explored by researchers for the quasi-cyclic low density parity check (LDPC) codes. In these architectures, the reconfigurab...
Jun Tang, Tejas Bhatt, Vishwas Sundaramurthy